(a) Field of the Invention
The present invention relates to a semiconductor memory device having a save register for a read data and, more particularly, to a semiconductor memory device implemented as a synchronous dynamic random access memory (SDRAM).
(b) Description of the Related Art
SDRAMs are increasingly used for a computer system because of its high-speed operation FIG. 1 illustrates a block diagram of a conventional SDRAM, and FIG. 2 is a signal timing chart of the SDRAM of FIG. 2. The conventional SDRAM comprises a peripheral circuit in a peripheral region of the SDRAM 1 for controlling read/write operations of a memory cell array 6. In the control of the memory cell array 6, the column access involves a clock delay, or CAS (column address strobe) latency, in a read cycle between the time instants of the input of a read command and the output of the read data.
In FIG. 1, SDRAM 1 comprises an address/command input section 2, a control section 3, a Y-address latch/decode section 4, an X-address decode and ROW control section 5, a memory cell array 6, a data amplifier 7, a data-out latch 8, a data input section 9, a write buffer 10, and a data-out buffer 17, which operate in synchrony with an external clock signal. The clock signal 1501 input through a clock signal input terminal 15 is delivered within the SDRAM 1 through a clock signal line. The input of the address/command input section 2 is connected to external input terminals 11, whereas the input/output terminals 12 are connected to an external bus line. The control section 3 controls operations of the entire SDRAM 1.
The X-address decode and ROW control section 5, operating based on X-address/control signals 302 output from the control section 3, determines X-address of the specified memory cell in the cell array.6. Data are read from or stored in the memory cell by determining the cell address by the Y-address latch/decode section 4 and the X-address decode and ROW control section 5. The data amplifier 7 amplifies the data thus read out. The data-out latch 8 outputs the data amplified by the data amplifier 7 to data input/output terminals 12 via the data-out buffer 17 in synchrony with the clock signal. The data input section 9, operating in synchrony with the clock signal, latches write data input through the input/output terminals 12. The write buffer 10 writes the write data to the specified memory cell in the memory cell array 6. A plurality of serial Y-address latch/decode sections 4 and data-out latches 8 may be disposed in the case of a large CAS.
Referring to FIG. 2, there is shown an example of read and write operations in the memory device of FIG. 1, wherein R1 to R11 shown on the row of CMD+ADD(11) are read commands and W1 to W8 are write commands. In a read cycle, a read command R1, for example, input through the address/command input terminals 11, is latched in the address/command input section 2 in synchrony with the clock signal input through the clock input terminal 15.
Subsequently, the read address (column address) is determined by latching the Y-address in the Y-address latch/decode section 4 in synchrony with the clock signal, and the read data is output from the specified memory cell. The read data is then amplified by the data amplifier 7 and, after being latched in the data-out latch 8 in synchrony with the next clock signal, output through the data input/output terminals 12 via the data-out buffer 17.
In the conventional SDRAM, output of the read data through the data input/output terminals 12 starts at the third clock counted from the first clock for latching the address and the command signals. The actual reading of the data starts at the fourth clock, thereby involving a CAS latency, as shown in FIG. 2.
On the other hand, when a write command W1, for example, is input through the address/command input terminals 11, the write command W1 is latched in the address/command input section 2 in synchrony with the clock signal. Then, the write address (column address) is determined by latching the Y-address in the Y-address latch/decode section 4 in synchrony with the clock signal. The write data, input through the data input/output terminals 12 in synchrony with the clock signal, is input and written in the specified memory cell through the write buffer 10 after being latched by the data input section 9. The process from latching the write command signal to the completion of the write Operation is performed in two clocks.
With the conventional SDRAM of FIG. 1, a write command cannot be input until data being read out is delivered to outside the memory device due to the latency in a read cycle. Accordingly, there arises the problem that alternate read operations with write operations in the SDRAM significantly decreases the effective bandwidth of the data input/output terminals 12.
FIG. 3 illustrates a schematic diagram of another conventional semiconductor memory device implemented as a synchronous static random access memory (referred to as SSRAM, hereinafter), which is described in JP-A-7(1995)-182870. FIG. 4 shows a signal timing chart for the SSRAM of FIG. 3. An external address signal ADD shown in FIG. 4 is supplied to comparators 35 as an internal address signal W2ADD via a buffer circuit 21 and latch circuits 23, 25, 26 and 27. An output address signal is supplied from the latch circuit 23 to a multiplexer 34 as an internal address signal RADD via a latch circuit 31. An output signal from the latch circuit 26 is supplied to the multiplexer 34 and the comparators 35 as an internal address signal W1ADD via latch circuits 28, 29 and 30.
An external write-enable signal NWE is supplied via a buffer circuit 22 and a latch circuit 24 to a latch circuit 32, and latched therein. An output from the latch circuit 32 is supplied to the multiplexer 34, a read circuit 37 and a write circuit 38 of the memory cell array 36, and an AND gate 33 after inversion as an internal write-enable signal NWEin. An output signal from the latch circuit 32 is also supplied to an AND gate 42 via latch circuits 40 and 41 after inversion.
An internal clock signal PH1 obtained by receiving an external clock signal CLK through a buffer 56 is input to the other input terminals of the AND gates 33 and 42. An output signal PH1-WE from the AND gate 33 is supplied as a latch pulse to the latch circuits 25 and 28, and an output signal PH1-WED from the AND gate 42 is supplied as a latch pulse to latch circuits 53 and 55.
Among the I/O signals shown in FIG. 10, write data such as DW0 supplied from outside is latched by the latch circuit 53 via a buffer 52 as write data WD2. The latched data WD2 is further transferred via a buffer 54 to the latch circuit 55 and latched therein as write data WD1. The write data WD1, together with the write data WD2, is supplied to a multiplexer 45 as well as the write section 38.
One of the two comparators 35 outputs a high-level signal when the internal address signals W1ADD and RADD coincide. The other of the two comparators 35 outputs a high-level signal when the internal address signals W2ADD and RADD coincide. AND gates 43 and 44 receive output signals from the comparators 35 and the internal write-enable signal NWEin to output an H-level signal when both input signals are at H-level. The multiplexer 45 selects the write data WD1 and supplies the same to a multiplexer 47 when the output signal from the AND gate 43 is at H-level, or the write data WD2 when the output signal from the AND gate 44 is at H-level.
The multiplexer 47 outputs the data input from the multiplexer 45 when the output from an OR gate 46 making OR of the output signals from the AND gates 43 and 44 is at H-level, or outputs the read data from the read section 37 when the signal from the OR gate is at L-level. The output data from the multiplexer 47 is delivered to outside via latch circuits 48 and 49, and a tri-state buffer 50.
The multiplexer 34 selects the internal address signal W1ADD and supplies the same to a decoder 39 as an internal address signal WADD when the internal write-enable signal NWEin is at L-level, and selects the internal address signal RADD and supplies the same to the decoder 39 as an internal address signal AADD when NWEin is at H-level. In a read cycle, therefore, data read out from the memory cell array 36 by the read circuit 37 is delivered to outside based on the internal address signal RADD supplied to the decoder 39. In a write cycle, on the other hand, write data WD1 or WD2 supplied via the write circuit 38 is stored in the memory cell array 36 based on the internal address signal W1ADD supplied to the decoder 39.
The conventional SSRAM as described above may improve the bandwidth of data input/output by adjusting the read latency (three clocks) with the write latency (three clocks). This is achieved by storing write data and write address in the latch circuits 27, 30, 54 and 55, and performing a pipeline processing wherein the data stored in the latch circuits is supplied to the memory cell array 36 at the next write cycle in synchrony with the clock signal.
However, the difference between CAS latency in a read cyle and CAS latency in a write cycle is as high as three or four. If the latency difference is three, Y-address storage register must have a storage capacity as high as (Y-address length.times.3 bits), and the data storage register must have a storage capacity as high as (data length.times.3 bits) to adapt the latency difference. Thus, application of this configuration of the conventional SSRAM of FIG. 3 to a SDRAM, wherein write address and write data are stored and used during the next write operation, will result in a large chip size.